Group III-nitride based devices have many potential material advantages over silicon based devices for high power electronics applications. Amongst others, the advantages can include a larger band gap and breakdown field, high electron mobility in a two dimensional electron gas (2DEG) and low thermal generation current. However, large native substrates for group III-nitride semiconductors are not yet widely available. Currently, III-nitride films are grown by heteroepitaxy on suitable non-III-nitride substrates.
Substrates commonly used to support III-nitride films are silicon carbide, sapphire or silicon. Heteroepitaxy can be done with molecular beam epitaxy (MBE) or metal oxide chemical vapor deposition (MOCVD), and lately with hydride vapor phase epitaxy (HVPE). It can be difficult to grow high quality thick gallium nitride layers by heteroepitaxy; therefore, high voltage devices in gallium nitride are typically lateral devices with gallium nitride layers that are only a few microns thick. It can be difficult to accommodate a large voltage in a lateral device without spacing out the electrodes a relatively large distance. For a large blocking voltage across the source/gate and drain in a FET or across the anode and cathode in a diode, the spacing between the electrodes needed to sustain the voltage can be large. For example, a 1 kV device may have gate-drain electrode spacing of 10 μm or larger. This can cause high voltage lateral devices to have a larger area than an equivalent vertical device. Thus, substrate cost becomes an important issue commercially.
To reduce cost, silicon is the most desirable substrate for III-nitride layers. However, due to the large lattice and thermal mismatch between silicon and gallium nitride, it can be necessary to include nucleation and stress management layers in the device structures. These layers, often called the buffer layer and comprised of layers of AlxGa1-xN that can include superlattices, can have a high density of threading dislocations and other extended defects, along with a multitude of point defects that act as deep traps or dopants. An appropriate buffer layer, even for a lattice mismatched substrate, can result in films of acceptable quality above the buffer layer. However, the layers within the buffer layer can have a high concentration of defect levels in the bandgap. The bandgap defect levels can cause dispersion or current collapse due to electron trapping in these layers, leakage at high drain biases due to carrier generation in these layers, and reduce the breakdown voltage of the device.
FIG. 1 shows an approach used to confine electrons to the channel. The III-nitride stack of FIG. 1(a) is for n-channel devices on the cation face, the preeminent form of III-nitride structure currently being used for fabricating HEMTs. The stack can be used to form a lateral device in which external biases modulate field and current in the active layer. The device structure includes a substrate 101 on which a buffer layer 102, which may include nucleation and stress management layers, is grown by heteroepitaxy. The active layer, which includes a channel layer 103 that has a 2DEG 104, is on the buffer layer 102. A barrier layer 105 whose dipole charge enables the formation of the 2DEG and confines the electrons to the channel layer is on an opposite side of the channel layer 103 from the buffer layer 102. Insulation and metallization layers are deposited and patterned to form the device (not shown).
Referring to FIG. 1(b), there can be a step in the conduction band edge (ΔEC) going from the channel layer to the buffer layer. As shown in the band diagram along the plane YY1, a higher conduction band edge in the buffer layer can prevent carrier injection and trapping in the buffer layer as long as the barrier height is larger than the energy of the electrons impinging on it. Electron e1 with energy less than the barrier height gets reflected back at the barrier (schematic trajectories r1 and r′1) while electron e2 with energy greater than the barrier gets injected into the barrier where it could get trapped (schematic trajectory r′2) or get collected by the substrate contact on the other side of the barrier (schematic trajectory r″2). FIG. 1(b) only shows trapping processes in the buffer layer. However, the defects that form deep levels in the buffer layer also diffuse into the channel layer where they can readily trap electrons and cause current collapse.